FIG. 4 shows a conventional motor driving circuit. A coil as a load is coupled to the outputs of transistors NMOS 101 and NMOS 102 which are provided at the final output stage of this motor driving circuit. The motor control is performed by controlling the current supplied to the coil (The motor is not shown in the drawing). The configuration of the motor driving circuit shown in FIG. 4 will be described as follows. The NMOS 101 and the NMOS 102 are drivers provided at the final output stage and a common node of the source of NMOS 101 and the drain of NMOS 102 constitutes the final output. A supply voltage 107 is coupled to the drain of NMOS 101, while an output from a common drain node of PMOS 103 and NMOS 104 is coupled to the gate of NMOS 101. Further, a logic circuit 112 is coupled to the gate of NMOS 102, and a logic circuit 110 is coupled to the gate of the PMOS 103 respectively. Here, Zener diodes 108 and 109 functioning as clamp circuits are also used for ensuring a potential difference (VgS) between the gate and the source of NMOS 101 and a potential difference between the gate and the source of NMOS 104 until a reverse saturation current starting to be supplied respectively to the Zener diodes. At the same time, the Zener diodes are also functioning to prevent an over-voltage being applied to respective VgS of NMOS 101 and the NMOS 104. Finally, the gate of a PMOS 105 is coupled to a logic circuit 111 and the gate voltage of an NMOS 106 is coupled to a logic circuit 113. The final output is determined in accordance with the state of an input voltage from the logic circuits 110, 111, 112 and 113.
Now, an operation of the conventional motor driving circuit shown in FIG. 4 will be described below together with a voltage wave form diagrams of the motor driving circuit shown in FIG. 5. The wave form diagram of FIG. 5 shows, from an upper part, the low/high of the final output and the gate voltages of NMOS 101, the NMOS 102, the PMOS 103, the NMOS 104, the PMOS 105 and the NMOS 106 (that is, when the gate voltage of NMOS is high, the NMOS is turned on). In a section of (A) shown in FIG. 5, the final output is high. That is, the NMOS 101 as the driver constituting the final output stage is in on-state and the NMOS 102 is in off-state. Since the NMOS 101 is in on-state, the output from the common drain node of the PMOS 103 and the NMOS 104 is high. Consequently, the PMOS 103 is in on-state and the NMOS 104 is in off-state, that is, the gate voltage of the PMOS 103 and the NMOS 104 is low. Further, since the NMOS 104 is in off-state, the PMOS 105 is in on-state and the NMOS 106 is in a state of being tuned off. Further, in a section (B) shown in FIG. 5, the final output is low. In comparison with the section (A) in which the final output is high, the on/off states of NMOS 101, the NMOS 102, the PMOS 103, the NMOS 104, the PMOS 105 and the NMOS 106 and the states of input voltage to the gates of the respective transistors come to be the inverted states to those described in the case of the section (A).
The final output is fed back to the gate of NMOS 101 through the Zener diode 108, and to the gate of NMOS 104 through the Zener diode 109 and the source of NMOS 104 in order to control the gage voltage of NMOS 101 based on the source of NMOS 101 and the source of NMOS 104 as the references. Thus, the abnormal state of the final output can be detected by the transistor used for the motor driving circuit, on top of this, using the transistors together with the clamp circuits eliminates the need of designing the devices used for the motor with a high voltage tolerance level.
In the above-described circuit operation, as to the high/low switching of the low of the final output from the common node of NMOS 101 and the NMOS 102, the NMOS 104 needs to be switched to on from off-state to on-state. On the other hand, in order to switch the final output from Low to High, the NMOS 104 needs to be switched from on-state to off-state. Accordingly, one of the requirements of rapid reflection of the input is to the final output is to switch the NMOS 104 on and off rapidly, that is, the gate capacity and the parasitic capacity of NMOS 104 need to be charged and discharged at high speed.
Here, from Q=IT (Q: quantity of electric charge; I: current, T: time), quick electric charge of the gate capacity and the parasitic capacity of a MOS transistor can be performed by increasing the quantity of current that is supplied to the gate of the MOS transistor. In order to solve this problem, current flow amount from the drain of the PMOS 105, which is coupled to NMOS 104, needs to increase so as to improve a charging speed of the gate capacity and the parasitic capacity of NMOS 104. On the other hand, if the drain current of the drain of NMOS 106 coupled to the gate of NMOS 104 is increased, a discharging speed of the gate capacity and the parasitic capacity of NMOS 104 can be improved. Therefore, from a current equation of a MOS transistor in a saturated state Ids=K(Vgs−Vth)2 (K: constant, Vth: threshold voltage of PMOS), one of the solution is to increase the drain current of the PMOS 105 so as to increase Vgs, however, since a drive operation with a low electric power consumption is desirable today, it is not preferable to increase a supply voltage 115 coupled to a source. In the above-described formula, as K is a constant proportional to the width of the gate forming the transistor, the quantity of current can be also increased by expanding the width of the gate. Further, from I=R/V in accordance with the Ohm's law, by lowering the resistance value of a resistance 114, which is coupled to the source of the PMOS 105, it is possible to increase the current from the drain of the PMOS 105.